1. Field of the Invention
The present invention relates to the field of telephone line modems, and more particularly, to a symbol timing recovery circuit in a telephone line modem receiver.
2. Description of the Related Art
With increasing attention being paid to home networking technology in recent years, development efforts have been proceeding in a variety of ways. One target of recent efforts, which is expected to be in high demand in the future, is a method of using telephone lines to implement home networking.
A symbol synchronization algorithm is a core technological element of a telephone line modem. Symbol synchronization refers to recovery of the timing of a symbol, that is, determination of an optimal sampling time when sampling a received analog signal in order to convert it into a digital signal.
FIG. 1 is a schematic block diagram showing a receiver of a conventional telephone line modem. In general, a received signal, which is input to the receiver of a telephone line modem, is an analog signal and is sent through a band pass filter (BPF) 102. Next, a gain of the signal is adjusted in an automatic gain controller (AGC) 104. An output signal of the AGC 104 is converted into a digital signal, by being sampled with a sampling frequency (Fs) in an analog-to-digital converter (A/D) 106. The output digital signal is then converted into a baseband signal by multiplication by a signal having a central frequency (Fc) in a mixer 108. The baseband signal is subsequently filtered in a low pass filter (LPF) 110, and then sent through a symbol timing recovery circuit 112, a frame synchronization unit 114, an equalizer 116, a carrier wave restoration circuit 118, a preamble generator/slicer 120, a channel decoder 122, and a deframe processor 124, and then is finally restored into information data.
Since the functions and operations of the elements of a conventional telephone line modem receiver are well-known to those skilled in the art, detailed explanation will be omitted. Among the elements of a telephone line modem, the symbol timing recovery circuit is of particular focus in the present invention.
Several algorithms for symbol synchronization have already been introduced, and symbol timing recovery circuits of the prior art simply apply these known symbol synchronization algorithms to a telephone line modem. However, symbol timing recovery circuits according to the prior art are vulnerable to clock instability and thus lack stability in symbol timing recovery. Since there is very low probability of a frequency offset occurring in a telephone line channel, clock instability occurring in an oscillator of a transmission/reception terminal accounts for the vast majority of the frequency offset. Therefore, a timing recovery circuit which is insensitive to clock instability and can stably estimate a timing offset is needed. SUMMARY OF THE INVENTION
In accordance with the present invention, a timing estimator which can stably estimate a timing offset for a telephone line modem is provided. Additionally, an interpolator is provided which can interpolate a received signal without dropping or reiteration, by overcoming clock instability. Furthermore, a timing recovery circuit for a telephone line modem which comprises the timing estimator and the interpolator is provided.
According to an aspect of the present invention, there is provided a symbol timing estimating circuit which estimates a symbol timing offset in a telephone line modem receiver, the symbol timing estimating circuit comprising a timing offset estimating unit which performs an operation on a received sample signal, estimates a timing offset, and outputs the estimated timing offset, wherein the timing offset estimating unit, in response to a control signal, estimates the timing offset in units of a predetermined window size, outputs a timing offset estimated for each symbol for a first window interval, and thereafter outputs a timing offset estimated in an immediately previous window interval for a current window interval, and a control signal generation unit which generates the control signal for, controlling the operation of the timing offset estimating unit in response to a carrier sense signal.
It is preferable that the timing offset estimating unit comprises an operator which calculates and outputs a square of the received sample signal, a mean estimator which calculates a mean of the output of the operator in units of the window size, in response to a reset signal, and a memory unit which maintains the mean value output from the mean estimator in response to a hold signal.
It is preferable that the control signal generation unit begins counting from a time when the carrier sense signal is received, activates a reset signal whenever the count value is a multiple of the window size, and activates a hold signal when the count value is greater than the window size and the reset signal is inactivated.
According to another aspect of the present invention, there is provided an interpolator circuit which performs interpolation using input samples in a telephone line modem receiver, the interpolator circuit comprising a plurality of shift registers which are serially connected and output the input samples in parallel in units of a predetermined plural number of input samples, by sequentially delaying for an input sample period and then outputting the input samples, a controller which selects four adjacent samples in a predetermined location among the plurality of input samples in response to an integer timing offset, and an interpolator which performs interpolation using the input samples selected by the controller and outputs output samples, in response to a fractional timing offset.
It is preferable that the number of input samples for each symbol is 4.
It is preferable that the controller selects 4 adjacent input samples immediately preceding the current location by a distance of 4 samples when the integer timing offset varies from 1 to 2, and selects 4 adjacent input samples immediately succeeding the current location by a distance of 4 samples when the integer timing offset varies from 2 to 1.
According to another aspect of the present invention, there is provided a symbol timing recovery circuit which recovers a symbol timing in a telephone line modem receiver, the symbol timing recovery circuit comprising a timing estimator which performs an operation on input samples and estimates a timing offset of a received symbol, wherein the timing estimator outputs a timing offset estimated for each symbol for a first window interval, and thereafter outputs a timing offset estimated in an immediately previous window interval for a current window interval, and an interpolator which performs interpolation using the input samples. Here, the interpolator comprises a plurality of shift registers which are serially connected, and output the input samples in units of a predetermined plural number of input samples, by sequentially delaying for an input sample period and then outputting the input samples, a control unit which selects four adjacent samples in a predetermined location among the plurality of input samples in response to an integer timing offset, and an interpolation unit which performs interpolation using the input samples selected by the controller and outputs output samples, in response to a fractional timing offset.
It is preferable that the timing estimator comprises a timing offset estimating unit which estimates the timing offset in units of a predetermined window size in response to a control signal, and a control signal generation unit which generates the control signal for controlling the operation of the timing offset estimating unit in response to a carrier sense signal.